A configuration has been disclosed that performs reception processing by means of direct discrete time sampling of a high-frequency signal with the aim of achieving small size and low power consumption of a receiver and integrating the analog signal processing section and digital signal processing section (see Non-patent Document 1 and Patent Document 1, for example).
An example of the configuration and operation of a discrete time direct sampling circuit that uses conventional discrete time processing is described below using FIG. 1. Overall, FIG. 1 shows a discrete time filter sampling circuit. The discrete time direct sampling circuit is provided with voltage-to-current converter (TA) 1, sampling switch 2, history capacitor (CH) 3, rotation capacitor group 4a through 4h, buffer capacitor (CB) 5, damping switch 6, reset switch 7, integration switch group 8a through 8h, discharge switch group 9a through 9h, and digital control unit 10.
Voltage-to-current converter (TA) 1 converts a received radio frequency (RF) signal to a current, and outputs it as an analog RF current signal. Sampling switch 2 is composed of an FET, for example, and samples an input analog RF current signal according to local frequency signal input (LO). History capacitor (CH) 3 charges a charge supplied by a current output from sampling switch 2. Rotation capacitor group 4a through 4h is connected in parallel to history capacitor 3 and buffer capacitor 5 via a plurality of kinds of switches, and is configured by means of a plurality of rotation capacitors (CR) that charge or discharge a charge according to on/off control of the switches. Buffer capacitor (CB) 5 is connected in common to the charges charged by the plurality of rotation capacitors 4, and buffers a charge signal. Damping switch 6 switches the connections between rotation capacitors 4a through 4h and buffer capacitor 5 on and off. Reset switch 7 grounds the charges accumulated in rotation capacitors 4 after charge sharing with buffer capacitor 5. Integration switch group 8a through 8h is composed of a plurality of integration switches, and switches the connections between history capacitor 3 and the rotation capacitors in rotation capacitor group 4a through 4h on and off. Discharge switch group 9a through 9h is composed of a plurality of discharge switches, and switches the connections between the rotation capacitors in rotation capacitor group 4a through 4h and buffer capacitor 5 on and off.
Damping switch 6, reset switch 7, integration switch group 8a through 8h, and discharge switch group 9a through 9h, are configured by means of FETs (n-type), for example. An n-type FET is turned on (energized) when the gate voltage is high, and turned off (shut off) when the gate voltage is low.
Digital control unit 10 generates and supplies control signals to integration switch group 8a through 8h, discharge switch group 9a through 9h, damping switch 6, and reset switch 7.
As an example, a case is assumed here in which eight rotation capacitors CR are provided, and eight integration switches 8a through 8h and eight discharge switches 9a through 9h are provided accordingly, with letters “a” through “h” appended in alphabetical order to the respective configuration element numbers. Actually, it is also possible to use a configuration that performs differential operation, and such a configuration is disclosed in Patent Document 1, but a description of this configuration is omitted here for the sake of brevity.
FIG. 2 shows a timing chart of the control signals generated by digital control unit 10. A local frequency signal (LO) is supplied to the gate of sampling switch 2. Control signals S1 through S8 are supplied to integration switches 8a through 8h respectively. Control signal SAZ is supplied to the gates of discharge switches 9a through 9d, and control signal SBZ is supplied to the gates of discharge switches 9e through 9h. Control signal D is supplied to the gate of damping switch 6, and control signal R is supplied to the gate of reset switch 7.
The operation of the discrete time direct sampling circuit shown in FIG. 1 will now be described. Voltage-to-current converter 1 converts an input analog RF signal to an analog RF current signal, and outputs this signal to sampling switch 2. The analog RF current signal is sampled at sampling switch 2 by means of local frequency signal LO having virtually the same frequency as the analog RF current signal, and is made temporally discrete discretized signals by having the charges integrated by history capacitor 3 and rotation capacitors 4a through 4h. 
The discrete signals are integrated over a time period longer than the local frequency signal LO clock by a capacitor configured by means of history capacitor 3 and one of rotation capacitor group 4a through 4h connected in parallel. By this means, filter processing and decimation are performed.
Specifically, first, integration switch 8a is turned on by control signal S1, rotation capacitor 4a is connected to history capacitor 3, and the charge applied to the aforementioned two capacitors is integrated over a time period during which control signal S1 is high (for example, eight cycles of local frequency signal LO).
When control signal S1 goes low, the connection of history capacitor 3 to rotation capacitor 4a is turned off, and connection to rotation capacitor 4b is turned on by means of control signal S2. Rotation capacitor 4b integrates a charge supplied by the discrete signal current over a period during which control signal S2 is high, and then turns off the connection to history capacitor 3. Similarly, rotation capacitors 4c through 4h are connected in turn to history capacitor 3 for eight local frequency signal LO cycles each by means of control signals S3 through S8, and the charge supplied by the discrete signal current is integrated by the two capacitors.
In this way, the charges supplied by the currents of discrete signals equivalent to eight local frequency signal LO cycles are integrated, and an 8-tap FIR (Finite Impulse Response) filter characteristic is realized. Also, since a one-sample charge amount is obtained by integrating signals for eight local frequency signal LO cycles, the sampling rate is decimated to ⅛. The functional section that realizes this filter characteristic will be referred to as a first FIR filter.
Also, an IIR (Infinite Impulse Response) filter characteristic is realized by rotation capacitors 4a through 4h being connected in turn to history capacitor 3. The functional section that realizes this filter characteristic will be referred to as a first IIR filter.
Next, by having discharge switches 9a through 9d turned on by control signal SAZ, conduction is effected between rotation capacitors 4a through 4d and buffer capacitor 5, and the charges charged by rotation capacitors 4a through 4d are shared with buffer capacitor 5. As a result, part of the charges of rotation capacitors 4a through 4d respectively moves to buffer capacitor 5, and the charge amounts are combined. After charge sharing between rotation capacitors 4a through 4d and buffer capacitor 5, damping switch 6 is turned off by control signal D, and the charge sharing state is terminated. Then reset switch 7 is turned on by control signal R, and charges remaining in rotation capacitors 4a through 4d are reset by grounding.
In this way, a 4-tap FIR filter characteristic is realized by part of charges charged in rotation capacitors 4a through 4d moving to buffer capacitor 5 and being combined. As digital signals equivalent to four samples are combined and a one-sample digital signal is output, the sampling rate is decimated to ¼.
For rotation capacitors 4e through 4h, similarly, discharge switches 9e through 9h are turned on by control signal SBZ, and part of the charge charged in each rotation capacitor is shared with buffer capacitor 5, whereby 4-tap FIR filter processing and ¼ decimation are performed. This filter characteristic will be referred to as a second FIR filter.
Also, an IIR filter characteristic is realized by placing the rotation capacitor 4a through 4d and 4e through 4h groups alternately in a charge sharing state with buffer capacitor 5. This filter effect will be referred to as a second IIR filter.
FIG. 3 shows filter characteristics when the frequency of local frequency signal LO is 2.4 GHz, the capacitance of history capacitor 3 is 15 pF, the capacitance of each of rotation capacitors 4a through 4h is 0.5 pF, the capacitance of buffer capacitor 5 is 15 pF, and the transconductance of voltage-to-current converter 1 is 7.5 mS. FIG. 3A shows the characteristic of the first FIR filter, FIG. 3B the characteristic of the first IIR filter, FIG. 3C the characteristic of the second FIR filter, FIG. 3D the characteristic of the second IIR filter, FIG. 3E the characteristic of the overall discrete time direct sampling circuit, and FIG. 3F a magnification of the characteristic in FIG. 3E in the frequency range in the vicinity of 2.4 GHz. DC gain has been normalized at 0 dB.
As described above, a discrete time direct sampling circuit outputs a signal for which filter processing with a characteristic combining the characteristics of a first FIR filter, first IIR filter, second FIR filter, and second FIR filter has been executed is output to a later-stage circuit.
Patent Document 1: US Patent Application Laid-Open No. 2003/0035499 Specification, “Direct Radio Frequency Sampling with Recursive Filtering Method”
Non-patent Document 1: R. B. Staszewski et al, “All-Digital TX Frequency Synthesizer and Discrete-Time Receiver for Bluetooth Radio in 130n-nm CMOS”, IEEE Journal of Solid-State Circuits, VOL. 39, No. 12, December 2004 (pp 2284-2287, FIG. 12-FIG. 16)